1. Field of the Invention
This invention relates to phase-locked loops, and more particularly to adjusting the phase of a phase-locked loop output.
2. Description of the Related Art
In optical communication systems, line cards compliant with standards such as Synchronous Optical Network (SONET) or Synchronous Digital Hierarchy (SDH) (the European counterpart to SONET), utilize clock generation circuits to generate clocks used in data transmission and reception. In such clock generation circuits, a phase-locked loop (PLL) receives an input reference clock and generates one or more high speed clocks suitable for use in transmitting or receiving data in a SONET(or SDH) based system. According to one aspect of such a communication system, multiple reference clocks may be supplied to a clock generation circuit to provide a variety of capabilities, including redundancy. When the PLL in the clock generation circuit switches from using one input reference clock to using another input reference clock, the amount of phase change allowed as a result of the switch is restricted, since large phase changes in the output clock due to switching input clocks can lead to problems such as transmission errors.
Even with such restrictions on allowed phase changes, such phase changes can accumulate causing a clock at a source of an optical transmission, which may be kilometers away from a destination, to be become sufficiently out of phase with the clock at the destination that adjusting the phase of one of the clocks would be desirable. In addition clocks are subject to long term wander due to such factors as temperature and voltage variations, which can also lead to phase differences between clocks. Thus, the ability to programmably adjust the phase is desirable.